A conventional method for counting charges passing in and out of a battery (referred to as “coulomb counting”) includes generating a sense voltage linearly proportional to a current (e.g., a charging current or a discharging current) of the battery, using a voltage-to-frequency converter to convert the sense voltage to a frequency signal linearly proportional to the sense voltage, and counting a number of waves/pulses of the frequency signal to generate a count value. The count value can represent an amount of accumulation of electric charges passing in and out of the battery.
FIG. 1 illustrates a circuit diagram of a conventional voltage-to-frequency converter 100. As shown in FIG. 1, the voltage-to-frequency converter 100 includes a sense resistor R′SEN, an integrator (e.g., a combined circuit of a resistor R′INT, an integrating capacitor C′INT, and an operational amplifier (OPA) 112; hereinafter, integrator (R′INT, C′INT, 112)), comparators 114 and 116, compensation circuitry (e.g., a combined circuit of capacitors CP1 and CP1, and switches M1-M8), and a control circuit 150.
The sense resistor R′SEN senses a battery current I′BAT of a battery 152 to generate a sense voltage V′SEN. The integrator (R′INT, C′INT, 112) integrates the sense voltage V′SEN to generate an integral result V′INT. The integral result V′INT represents an integral value of the sense voltage V′SEN, and therefore represents an integral value of the battery current I′BAT. The comparators 114 and 116 compare the integral result V′INT with voltage references V′H and V′L (V′L<V′H) to generate a train of pulse signals CMP′H and CMP′L. The control circuit 150 controls the switches M1-M8 according to the pulse signals CMP′H and CMP′L. A frequency f′CMP of the pulse signals CMP′H or CMP′L represents the battery current I′BAT.
By way of example, if the battery 152 is in a charging mode, then the sense voltage V′SEN labeled in FIG. 1 has a positive value, and the integral result V′INT decreases because of integration of the positive sense voltage V′SEN. When the integral result V′INT decreases to the voltage reference V′L, the comparator 116 generates a pulse signal CMP′L, and the control circuit 150 turns on a first group of switches M1, M4, M6 and M7, and turns off a second group of switches M2, M3, M5 and M8. Hence, the capacitor CP1 provides an amount of compensation charges Q′REF to the integrating capacitor C′INT through the inverting input terminal 154 of the OPA 112 to increase the integral result V′INT, and the capacitor CP2 is charged by the voltage V′REF to store an amount of compensation charges Q′REF. The increased integral result V′INT continues to decrease because of the integration of the positive sense voltage V′SEN. When the integral result V′INT decreases to the voltage reference V′L, the comparator 116 generates a next pulse signal CMP′L, and the control circuit 150 turns off the first group of switches and turns on the second group of switches. Hence, the capacitor CP2 provides the stored compensation charges Q′REF to the integrating capacitor C′INT through the terminal 154 to increase the integral result V′INT, and the capacitor CP1 is charged by the voltage V′REF to store an amount of compensation charges Q′REF. Thus, if the battery 152 is in a charging mode, then the control circuit 150 alternately turns on the first group of switches and the second group of switches, and the comparator 116 generates a train of pulse signals CMP′L at a frequency f′CMP that is linearly proportional to the charging current I′BAT. Similarly, if the battery 152 is in a discharging mode, then the control circuit 150 alternately turns a third group of switches M1, M2, M7 and M8 and a fourth group of switches M3, M4, M5 and M6, and the comparator 114 can generate a train of pulse signals CMP′H at a frequency f′CMP that is linearly proportional to the discharging current I′BAT. The frequency f′CMP of the trigger signals CMP′H/CMP′L can be used for the abovementioned coulomb counting.
However, the voltage-to-frequency converter 100 has some shortcomings. For example, the frequency f′CMP may have error caused by an input voltage offset V′OS of the OPA 112. Thus, a count value obtained by counting a number of the pulse signals CMP′H/CMP′L may have error caused by the input voltage offset V′OS.
Additionally, because the OPA 112 controls its inverting input terminal 154 and its non-inverting input terminal 156 to have the same voltage level, and the inverting input terminal 154 receives either a voltage level of V′REF or a voltage level of −V′REF from the capacitors CP1 and CP1, a voltage level at the non-inverting input terminal 156, which is also a terminal 156 of the sense resistor R′SEN, should be neither relatively high nor relatively low compared with the voltage levels V′REF and −V′REF. Because the voltage V′REF is relatively small compared with a voltage level at a positive terminal of the battery 152, the voltage level at the terminal 156 of the sense resistor R′SEN should be relatively small. Thus, the sense resistor R′SEN can be placed at the negative terminal of the battery 152 and cannot be placed at the positive terminal of the battery 152. In some situations, it would be beneficial to place the sense resistor R′SEN at the positive terminal of the battery 154. For example, there may be a thermistor (not shown) connected to the negative terminal of the battery 152 to measure temperature of the battery 152, and a sense resistor R′SEN placed at the negative terminal of the battery 152 may cause error in the measurement of the temperature. Placing the sense resistor R′SEN at the positive terminal of the battery 152 can avoid this error.
Moreover, the compensation circuitry in the voltage-to-frequency converter 100 uses two capacitors CP1 and CP1 to provide compensation charges to the integrator (R′INT, C′INT, 112). It would be beneficial to use one capacitor instead of two capacitors to provide compensation charges, so as to reduce the cost and size of the compensation circuitry.
Furthermore, when the capacitor CP1 provides compensation charges to the integrator (R′INT, C′INT, 112), the capacitor CP1 attempts to apply a voltage level V′REF or −V′REF to the inverting input terminal 154 of the OPA 112 that is different from a voltage level, e.g., zero volts, at the non-inverting input terminal 156 of the OPA 112. Because the OPA 112 controls the terminals 154 and 156 to have the same voltage level, a relatively big current may be generated by the OPA 112 to flow through the capacitors C′INT and CP1 to discharge the capacitor CP1, so as to reduce the voltage level V′REF or −V′REF of the capacitor CP1 to zero volts relatively quickly. This requires that the OPA 112 has a relatively high sensibility, and is able to generate and sustain a relatively big current. Such an OPA is relatively expensive and consumes relatively high power.
FIG. 2 illustrates a circuit diagram of a conventional coulomb counter 200. The coulomb counter 200 includes a sense resistor R′SEN, a counter 262, and a voltage-to-frequency converter. The voltage-to-frequency converter includes switches S1-S4, an integrator (e.g., a combined circuit of a resistor R′INT, a capacitor C′INT, and an operational amplifier OPA 212; hereinafter, integrator (R′INT, C′INT, 212)), an RC filter (including a resistor RFLT and a capacitor RFLT), comparators 214 and 216, and a control logic & polarity detection module 260.
The sense resistor R′SEN generates a sense voltage V′SEN1 indicative of a battery current I′BAT. The switches S1-S4 receive the sense voltage V′SEN1 and provide a voltage V′SEN2 to the integrator (R′INT, C′INT, 212). The integrator (R′INT, C′INT, 112) integrates the voltage V′SEN2 to generate an integral result V′INT. The integral result V′INT ramps up and down alternately, under control of the switches S1-S4. The comparators 214 and 216 compare the integral result V′INT with voltage references V′H and V′L (V′L<V′H) to generate trigger signals CMP′H and CMP′L, alternately. The module 260 controls the switches S1-S4 according to the trigger signals CMP′H and CMP′L such that the voltage V′SEN2 alternates between a voltage level of V′SEN1 and a voltage level of −V′SEN1. A frequency f′CMP at which the trigger signals CMP′H and CMP′L alternate represents the battery current I′BAT. The counter 262 counts a number of the trigger signals CMP′H and CMP′L to generate a count value representing an amount of accumulation of electric charges in the battery current I′BAT.
By way of example, in a situation when the battery current I′BAT flows through the sense resistor R′SEN from the terminal labeled “CS+” to the terminal labeled “CS−,” the sense voltage V′SEN1 labeled in FIG. 2 has a positive value. The module 260 can turn on the switches S1 and S4 and turn off the switches S2 and S3, and therefore the integrator (R′INT, C′INT, 212) integrates the voltage level of V′SEN1 to decrease the integral result V′INT. When the integral result V′INT decreases to the voltage reference V′L, the comparator 216 generates a trigger signal CMP′L, and the module 260 turns off the switches S1 and S4 and turns on the switches S2 and S3 in response to the trigger signal CMP′L. Hence, the integrator (R′INT, C′INT, 212) integrates the voltage level of −V′SEN1 to increase the integral result V′INT. When the integral result V′INT increases to the voltage reference V′H, the comparator 214 generates a trigger signal CMP′H, and the module 260 turns on the switches S1 and S4 and turns off the switches S2 and S3 in response to the trigger signal CMP′H. Thus, by alternately turning on the pair of switches S1 and S4 and the pair of switches S2 and S3 according to the trigger signals CMP′H and CMP′L, the coulomb counter 200 alternately generates the trigger signals CMP′H and CMP′L at an alternation frequency f′CMP that is linearly proportional to the battery current I′BAT. Similarly, when the battery current I′BAT flows through the sense resistor R′SEN from the terminal labeled “CS−” to the terminal labeled “CS+,” the coulomb counter 200 can also alternately generate trigger signals CMP′H and CMP′L at an alternation frequency f′CMP that is linearly proportional to the battery current I′BAT. The alternation frequency f′CMP can be used for coulomb counting.
However, the coulomb counter 200 has some shortcomings. For example, in a first time interval, the integrator (R′INT, C′INT, 212) can integrate a voltage level of V′SEN1 so that the integral result V′INT decreases from the voltage reference V′H to the voltage reference V′L; and in a second time interval, the integrator (R′INT, C′INT, 212) can integrate a voltage level of −V′SEN1 so that the integral result V′INT increases from the voltage reference V′L to the voltage reference V′H. The OPA 212 may have an input voltage offset V′OS, which causes a time difference between the first and second time intervals. Consequently, the alternation frequency f′CMP of the trigger signals CMP′H and CMP′L may have error caused by an integration of the voltage offset V′OS based on the time difference. A count value obtained by counting a number of the trigger signals CMP′H/CMP′L may have error caused by the input voltage offset V′OS.
Additionally, due to non-ideality of the comparators 214 and 216, there may be time delays in generation of the trigger signals CMP′H and CMP′L. This may result in error, e.g., a decrement, in the alternation frequency f′CMP of the trigger signals CMP′H and CMP′L. Comparators with relatively fast response speed may be used to reduce the error in the alternation frequency f′CMP. However, such comparators may be relatively expensive and consume relatively high power.
A coulomb counter that addresses the abovementioned shortcomings would be beneficial.